1. Field of the Invention
The present invention relates to a wafer transport apparatus arranged in a clean room and capable of transporting a wafer.
2. Description of the Related Art
In a semiconductor manufacturing process, wafers are processed in a clean room to improve yield and quality. However, today when the integration degree of elements is increasing, circuits are being miniaturized, and the size of wafers is increasing, management of a speck of dust in the whole clean room is becoming difficult from cost and technical viewpoints. For this reason, means for performing wafer transport and other processing, using a “mini-environment system” that improves the cleanliness of only a local space around a wafer instead of improving the cleanliness of the whole clean room, has recently been adopted. In the mini-environment system, a wafer in a storage container called a FOUP (Front-Opening Unified Pod) for transporting and retaining a wafer in a highly clean environment can be loaded into and unloaded from a wafer transport chamber through a load port.
In a state in which the FOUP is placed on the load port, a door section provided at the load port and a door provided at a back surface of the FOUP are simultaneously opened while the door section is in close contact with the door, and a wafer transport robot provided in the wafer transport chamber, such as an arm robot, can take out a wafer in the FOUP into the wafer transport chamber or store the wafer from the wafer transport chamber in the FOUP through the load port. The load port is arranged at a front surface of the wafer transport chamber. A wafer transported by the wafer transport robot from inside the FOUP into the wafer transport chamber through the load port. And the wafer is transported to a semiconductor processing chamber (semiconductor processing apparatus) which subjects wafers to a semiconductor process (e.g., processing and cleaning) via a load lock chamber arranged at a back surface of the wafer transport chamber. After being subjected to appropriate processing in the semiconductor processing chamber, the wafer is transported to the load lock chamber and wafer transport chamber in this order and is stored in the FOUP on the load port.
In order to improve the processing efficiency (throughput) of a wafer to undergo the above-described transport procedure, a technique is disclosed for arranging a plurality of load ports at a front surface of a wafer transport chamber, arranging in the wafer transport chamber one wafer transport robot capable of sliding in a direction in which the load ports are installed in parallel, and transporting a wafer between each load port and a semiconductor manufacturing apparatus (semiconductor processing chamber) by the wafer transport robot (see, e.g., Japanese Patent Laid-Open No. 2003-318244).
However, in the case of the configuration disclosed in Japanese Patent Laid-Open No. 2003-318244, both a wafer (unprocessed wafer) to be transported from one load port into a semiconductor processing chamber and a wafer (processed wafer) after predetermined processing to be transported from the semiconductor processing chamber to the other load port pass through a common wafer transport chamber. Accordingly, a contaminant such as residual gas deposited on the unprocessed wafer may adhere to the processed wafer or a FOUP to store the processed wafer in the wafer transport chamber. Additionally, a wafer transport robot sliding in the wafer transport chamber may stir a gaseous atmosphere in the wafer transport chamber, and the interior of the wafer transport chamber may be contaminated with the contaminant.